Devices and methods for radio-frequency voltage detection

ABSTRACT

Methods and apparatus are provided for detection of voltage levels of RF signals. A first voltage correction is provided based on a thermal voltage and a second voltage correction is provided based on a voltage difference between a detection transistor, used for the rectification of the RF signal, and a reference transistor, to which the RF signal is not supplied. Based on the first and second voltage corrections, a more accurate detector with greater linearity may be obtained. In an embodiment, the second voltage correction may be generated proportional to a hyperbolic tangent of the voltage difference between two transistors, obtained using an additional pair of transistors configured as a differential pair. Applications include the control of a power amplifier output in a wireless device.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. patent application Ser. No.15/207,485, filed Jul. 11, 2016, entitled “RADIO-FREQUENCY VOLTAGEDETECTION,” which claims priority to U.S. Provisional Application No.62/191,473, filed Jul. 12, 2015, entitled “RADIO-FREQUENCY VOLTAGEDETECTION,” the disclosure of which is hereby expressly incorporated byreference herein in its entirety.

BACKGROUND Field

The present disclosure relates to detectors of radio-frequency (RF)signals.

Description of the Related Art

In many radio-frequency (RF) applications it is advantageous to be ableto detect the power level of a signal. An approach is to detect theenvelope of a signal or its peak voltage.

For example, in some applications it is desirable to know the voltagelevel of a signal outputted from a power amplifier (PA) to providefeedback for controlling the outputted signal level. This may beincorporated into automatic gain control, wherein a feedback controlloop adjusts the gain of an amplifier based on the input signal powerlevel so the output signal power level is relatively constant.

An approach proposed by Meyer, R. G. in “Low-power monolithic RF peakdetector analysis,” IEEE Journal of Solid-State Circuits, vol.30, no.1,pp.65,67, January 1995, the entire contents being hereby incorporated byreference, makes use of a first bipolar transistor as rectifying elementand a second bipolar transistor to set up an offsetting dc voltage. Acircuit according to this approach is shown in FIG. 1. Meyer presents ananalysis for large square-wave input signals that relates the detectedvoltage to the input signal peak voltage plus an error term representedby V_(T)·In(2), in which V_(T) is the thermal voltage given by k_(B)T/q,in which q is the magnitude of the electrical charge of an electron,k_(B) is the Boltzmann constant and T is the absolute temperature, V_(T)having a value of approximately 25 mV at room temperature. It is furtherdisclosed that the V_(T)-dependent error term can be cancelled bydoubling the current in the second transistor relative to the firsttransistor. As the derived error term is only an approximation to thetrue error in a detector, practical implementations of this approach donot provide an exact measurement of the voltage level of the inputsignal, particularly for low voltage levels, having a non-linearresponse to the voltage level of the input signal.

Therefore it would be desirable to provide a detector with improvedaccuracy and/or linearity. It would further be desirable to provide sucha detector without greatly increasing the complexity, size or cost ofthe detector.

SUMMARY

In general, circuits, applications and methods are described fordetecting a voltage level of an RF signal.

In accordance with some implementations, the present disclosure relatesto a detector circuit for determining a peak voltage level of an RFsignal, the detector circuit comprising a detection transistorconfigured to receive the RF signal, and voltage correction circuitryconfigured to generate a first voltage correction based on the thermalvoltage and a second voltage correction based on a voltage differencebetween the detection transistor and a reference transistor that is notconfigured to receive the RF signal.

In some embodiments, the second voltage correction is based on a voltagedifference that is obtained without taking into account the firstvoltage correction. In some embodiments, the second voltage correctionis based on a voltage difference between an emitter of the detectiontransistor and an emitter of the reference transistor. In someembodiments, the second voltage correction is based on a voltagedifference between an emitter of the detection transistor and an emitterof the reference transistor.

In some embodiments, the second voltage correction increases withincreasing voltage difference from zero up to a threshold and does notincrease or increases at a lower rate with increasing voltage differenceabove the threshold. In some embodiments, the threshold is a softthreshold.

In some embodiments, the second voltage correction is based on a sigmoidfunction of the voltage difference. In some embodiments, the secondvoltage correction is based on a hyperbolic tangent of the voltagedifference divided by twice the thermal voltage.

In some embodiments, the detector circuit comprises first and secondreference transistors that are not configured to receive the RF signal,and the second voltage correction is based on a voltage differencebetween the detection transistor and the second reference transistor.

In some embodiments, the first voltage correction is V_(T)·In(2).

In some embodiments, the correction circuitry includes a differentialpair of transistors for generating the second correction voltage. Insome embodiments, the voltage inputs of the differential pair oftransistors are coupled to the emitters of the detection transistor andthe second reference transistor. In some embodiments, the correctioncircuitry is configured to produce, using the differential pair oftransistors, the second correction voltage based on hyperbolic tangentof a voltage difference between the detection transistor and the secondreference transistor.

In some embodiments, the differential pair of transistors includes twoemitter-coupled bipolar transistors or two source-coupled field-effecttransistors. In some embodiments, the correction circuitry includes atleast one current mirror stage to mirror the difference in collector ordrain currents of the differential pair to the first referencetransistor for generation of the second correction voltage.

In some embodiments, the differential pair of transistors includes twoemitter-coupled bipolar transistors. In some embodiments, the detectorcircuit includes a low-pass RC filter located between the emitter of thereference transistor and the base of a first transistor of thedifferential pair, and a matching resistor between the emitter of thesecond reference transistor and the base of the second transistor of thedifferential pair.

In some embodiments, the differential pair of transistors is connectedto a proportional-to-absolute-temperature current source. In someembodiments, the detection transistor and the first and second referencetransistors are connected to proportional-to-absolute-temperaturecurrent sources.

In some embodiments, the detection transistor and the first and secondreference transistors are NPN bipolar transistors, the RF input beingprovided to the base of the detection transistor.

In some embodiments, the detector circuit includes a bypass capacitorcoupled to a location between the base of the detection transistor andthe bases of the first and second reference transistors.

In accordance with some implementations, the present disclosure relatesto a semiconductor die comprising at least one detector circuit fordetermining a peak voltage level of a radio-frequency (RF) signal, thedetector circuit comprising a detection transistor configured to receivethe RF signal, and voltage correction circuitry configured to generate afirst voltage correction based on the thermal voltage and a secondvoltage correction based on a voltage difference between the detectiontransistor and a reference transistor that is not configured to receivethe RF signal.

In accordance with some implementations, the present disclosure relatesto an RF module comprising at least one semiconductor die comprising atleast one detector circuit for determining a peak voltage level of an RFsignal, the detector circuit comprising a detection transistorconfigured to receive the RF signal, and voltage correction circuitryconfigured to generate a first voltage correction based on the thermalvoltage and a second voltage correction based on a voltage differencebetween the detection transistor and a reference transistor that is notconfigured to receive the RF signal.

In accordance with some implementations, the present disclosure relatesto a wireless device comprising at least one RF module comprising atleast one semiconductor die comprising at least one detector circuit. Inthese implementations, the at least on semiconductor die comprises thedetector circuit for determining a peak voltage level of an RF signal,the detector circuit comprising a detection transistor configured toreceive the RF signal, and voltage correction circuitry configured togenerate a first voltage correction based on the thermal voltage and asecond voltage correction based on a voltage difference between thedetection transistor and a reference transistor that is not configuredto receive the RF signal.

In accordance with some implementations, the present disclosure relatesto a method of detecting a voltage level of an RF input signal. In theseimplementations, the method comprises rectifying the RF input signalwith a detection transistor, dc-offsetting the rectified RF input signalusing a reference transistor that is not configured to receive the RFinput signal, generating a first correction voltage based on the thermalvoltage, generating a second correction voltage that is based on avoltage difference between the detection transistor and the referencetransistor, and providing an output signal based on the voltage level ofthe RF input signal and the first and second correction voltages.

In some embodiments, the second correction voltage is generated based ona voltage difference between the detection transistor and the referencetransistor without taking into account the first correction voltage. Insome embodiments, the first voltage correction is V_(T)·In(2).

In some embodiments, the second voltage correction is based on a sigmoidfunction of a voltage difference between the detection transistor and asecond reference transistor. In some embodiments, the second voltagecorrection is based on a hyperbolic tangent of the voltage differencebetween the detection transistor and the second reference transistordivided by twice the thermal voltage.

In some embodiments, the method includes generating a differentialcurrent using a differential pair of transistors coupled to thedetection transistor and the second reference transistor, the generateddifferential current being proportional to the hyperbolic tangent of thevoltage difference between the detection transistor and the secondreference transistor divided by twice the thermal voltage, the secondvoltage correction being based on the differential current.

In some embodiments, the method includes low-pass filtering thedetection transistor voltage prior to generating the differentialcurrent based on the filtered detection transistor voltage.

The correction proposed by Meyer provides a constant term of V_(T)·In(2)to the detector response regardless of the voltage level of the RF inputsignal. It can be viewed as a first-order correction to the uncorrecteddetector output. The approach of the present disclosure can be viewed asan analogous to a second-order or higher order correction to thedetector output in that it is based on the detector output. At its mostgeneral, the present disclosure relates to the use of the detectoroutput to obtain a higher-order correction to the detector output thanobtained by Meyer. The higher-order correction may be a linear functionof the detector output or may be a non-linear function of the detectoroutput, such as a smooth non-linear function or a non-linear functionconsisting of two or more piece-wise linear portions.

In some circuits embodying aspects of the present disclosure, thedetector output used to obtain the higher-order correction is thedetector output that would have been obtained in the absence of thefirst (Meyer) voltage correction. This may be the uncorrected detectoroutput.

In some circuits embodying aspects of the present disclosure, themagnitude of the additional correction varies with the uncorrecteddetector output for input signals having uncorrected detector output ina particular range, and does not vary or does not substantially vary forinput signals having uncorrected detector output in another range.

In some circuits embodying aspects of the present disclosure, themagnitude of the additional correction may vary with uncorrecteddetector output for input signals having uncorrected detector outputlower than a threshold, and not vary or not vary substantially foruncorrected detector output above a threshold. The threshold may be ahard threshold in which the change between the two regimes is sharp or asoft threshold, in which the change between the two regimes is gradualover a transition range. Input signals of small peak voltage resultingin uncorrected detector output lower than the hard or soft threshold mayreceive an additional correction specific to the particular peak voltageof the input signal and input signals of higher peak voltage resultingin higher uncorrected detector output higher than the hard or softthreshold may receive an additional correction that is the sameadditional correction that would be received for input signals having aneven higher peak voltage as the additional correction does not changesubstantially with uncorrected detector output above the threshold. Inother circuits embodying aspects of the present disclosure, theadditional correction may continue to increase with increasinguncorrected detector output for uncorrected detector output above thethreshold, but at a slower rate than for uncorrected detector outputbelow the threshold.

In some circuits embodying aspects of the present disclosure, themagnitude of the additional correction may increase monotonically withincreasing input signal peak voltage or uncorrected detector output upto a threshold, and particularly a soft threshold, and above thethreshold the magnitude of the additional correction may be constant orsubstantially constant, not varying with further increase of inputsignal peak voltage or uncorrected detector output.

In some circuits embodying aspects of the present disclosure, theadditional correction may be a sigmoid function of uncorrected detectoroutput. The sigmoid function may be applied to the uncorrected detectoroutput and may provide alternative or additional improvement of thedetector output. A sigmoid function is a mathematical function having an“S” shape (sigmoid curve). For inputs greater than zero, the sigmoidcurve provides an increasing output with increase in input up to a softthreshold before becoming asymptotic to a constant value for arriving atthe constant value. One special case of a sigmoid function is thelogistic function defined by the formula 1/(1+e^(−t)). The logisticfunction is sometimes referred to as “the sigmoid function” but hereinthe term “sigmoid function” is used more generally to refer to the classof “S”-shaped curves. Other examples of sigmoid functions include theerror function, the arctangent, and the hyperbolic tangent. Othersigmoid functions may not have a definition over the entire domain butinstead may be defined piecewise, having a sigmoid curve over a range ofinterest. In some cases, a sigmoid curve can be obtained conveniently inan electronic circuit making use of nonlinear effects of a transistor. Apreferred sigmoid curve used in some detectors embodying aspects of thepresent disclosure is the hyperbolic tangent.

For purposes of summarizing the disclosure, certain aspects, advantagesand novel features of the inventions have been described herein. It isto be understood that not necessarily all such advantages may beachieved in accordance with any particular embodiment of the invention.Thus, the invention may be embodied or carried out in a manner thatachieves or optimizes one advantage or group of advantages as taughtherein without necessarily achieving other advantages as may be taughtor suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of this disclosure will be described in more detail by way ofexample only with reference to the accompanying drawings. The componentswithin the drawings are not necessarily to scale, emphasis instead beingplaced upon clearly illustrating principles.

FIG. 1 is a schematic of a prior art detector circuit according toMeyer's approach.

FIG. 2 is a schematic of a first circuit embodying an aspect of thepresent disclosure.

FIG. 3 is a schematic of a second circuit embodying an aspect of thepresent disclosure.

FIG. 4 is a schematic of a portion of a circuit embodying an aspect ofthe present disclosure

FIG. 5 is a plot comparing output of an uncorrected detector operatingat 313K with an ideal detector, a Meyer-corrected detector, and adetector corrected according to an aspect of the present disclosure, forinput RF signals of peak voltage in the range 0V to 1.4V.

FIG. 6 is a plot similar to FIG. 5, in which input RF signals arerestricted to the peak voltage range of 0V to 0.5V.

FIG. 7 is a plot of difference in response between an ideal detector andan uncorrected detector at operating at 313K, as well as the Meyercorrection, an additional correction embodying an aspect of the presentdisclosure, and the Meyer and additional, for input signals having peakvoltages in the range 0V to 1.4V.

FIG. 8 is a plot of linearity at different operating temperatures forthe uncorrected detector, the Meyer detector and a detector embodying anaspect of the present disclosure.

FIG. 9 is a flow diagram illustrating a technique for detecting avoltage level of an RF input signal embodying an aspect of the presentdisclosure.

FIG. 10 is a schematic of a third circuit embodying an aspect of thepresent disclosure.

FIG. 11 is a schematic of PFET and NPN current mirrors that form part ofthe circuit of FIG. 10.

FIG. 12 is a schematic of an RF system including a detector embodying anaspect of the present disclosure.

FIG. 13 is a schematic of a first packaged module embodying an aspect ofthe present disclosure.

FIG. 14 is a schematic of a second packaged module embodying an aspectof the present disclosure.

FIG. 15 is a schematic of a wireless device embodying an aspect of thepresent disclosure.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

Although described in the present disclosure with particular referenceto detecting the output of a power amplifier, detectors according to thepresent disclosure can be implemented in any system where it isdesirable to use a peak detector for measuring a peak voltage of asignal. While detectors embodying aspects of the present disclosure findparticular application for detecting RF input signals, such detectorsmay be used to detect the peak voltage of a lower frequency signal.

FIG. 1 is a schematic diagram of a circuit according to Meyer's approachand comprises two bipolar NPN transistors Q_(A) and Q_(B). Collectorterminals of Q_(A) and Q_(B) are connected directly to a supply voltageat Vcc. The base of Q_(B) is connected to Vcc via resistor R_(B) and thebase of Q_(A) is also connected to Vcc via resistor R_(A). The emitterof Q_(A) is connected to ground via, in parallel, current source I_(A)and capacitor C_(A). The emitter of Q_(B) is connected to ground via, inparallel, current source I_(A) and capacitor C_(B).

An RF input signal Vin is applied to the base of Q_(A), which acts as anonlinear rectifying element on the input signal. Transistor Q_(A)provides voltage V_(A) at its emitter. The second transistor Q_(B) setsup an offsetting dc voltage V_(B) at its emitter, so that the dc voltageVout, between the emitter of Q_(A) at voltage V_(A) and the emitter ofQ_(B) at voltage V_(B) is zero for zero ac signal input. The capacitorC_(B) at the emitter of Q_(B) acts as a filter to prevent Vcc noise fromcorrupting Vout. The capacitor C_(A) is the hold capacitor whose valueis set by the allowable droop ΔVout on Vout via equationsd/dt(Vout)=−I_(A)/C_(A) and so ΔVout=−I_(A)·Δt/C_(A), wherein d/dt(Vout)is the derivative of Vout with respect to time and Δt is approximatelyhalf the period of the input signal.

Meyer considers the operation of the circuit for an ideal square waveinput of peak amplitude V₁, assumed to be much larger than thermalvoltage V_(T). Under Meyer's assumptions, the current source forces theaverage current in Q_(A) to be equal to I_(A). As Q_(A) is onlyconducting for 50% of the time, Q_(A) will conduct with current 2·I_(A)when Vin is high (on the square wave input assumption) and not conductat all when Vin is low. Meyer suggests that, if I_(A)=I_(B), R_(A)=R_(B)and Q_(A) and Q_(B) are matched, then Vout=V₁−V_(T)·In(2). According toMeyer's analysis, the output voltage of the detector is equal to thepeak voltage of the input signal offset by the derived error term ofV_(T)·In(2), wherein V_(T) is the thermal voltage given by k_(b)T/q andIn(2) is the natural logarithm of 2. Meyer suggests that the derivederror term V_(T)·In(2) can be cancelled by making I_(B)=2I_(A) andR_(B)=R_(A)/2. According to Meyer's analysis, this will cause Vout toequal V₁ as desired.

The effect of making I_(B)=2I_(A) and R_(B)=R_(A)/2 is that the currentdensity in Q_(B) is twice that of the average current density in Q_(A),and equal to the current density while Q_(A) is conducting. By settingthe current densities in Q_(A) and Q_(B) in this way, a correction ofV_(T)·In(2) is provided to the uncorrected output of the dc offsetcorrected rectifying element Q_(A).

Increasing the current density in Q_(B) relative to the average currentdensity in Q_(A) compensates for the fact that Q_(A) might only beconducting for a portion of the time. Therefore the average currentdensity in Q_(B) may be increased relative to the average currentdensity in Q_(A) to provide a voltage correction. If the input signal isa square wave, i.e. the signal is at positive peak voltage for 50% atthe time and negative peak voltage for 50% of the time, then doubling ofthe current density in Q_(B) relative to the average current density inQ_(A) may be the appropriate degree of compensation.

Despite the Meyer's voltage correction of V_(T)·In(2), practicalimplementations of the schematic of FIG. 1 may not necessarily provide alinear output Vout that is equal to the peak RF voltage V₁ for all Vin.This is partly because the assumptions made by Meyer are not entirelyvalid for general signals.

FIG. 2 is a schematic diagram of a circuit embodying an aspect of thepresent disclosure. It is based on the circuit of FIG. 1 butincorporates an additional correction ΔV to the dc output voltage Voutprovided by current source Icorr between the base of Q_(B) and ground.The additional correction ΔV is given by the expressionk·I_(d)·tanh((V_(A)−V_(B))^(U)/(2·V_(T))), in which k is a factor havingdimensions of resistance, I_(d) is a current, tanh is the hyperbolictangent function, and (V_(A)−V_(B))^(U) is the difference in voltages onthe emitter of Q_(B) and Q_(A) if Meyer's correction to the currentsthrough Q_(A) and Q_(B) had not been applied, the superscript Usignifying “uncorrected”.

FIG. 3 is a schematic diagram of a circuit embodying an aspect of thepresent disclosure. It is based on the circuit of FIG. 2 andincorporates an additional reference transistor Q_(C), the collector ofwhich being directly connected to Vcc in the same manner as Q_(A) andQ_(B), and the base being connected to Vcc via resistor R_(C). Theemitter voltage has dc voltage V_(C) and is connected to ground via, inparallel, capacitor C_(C) and current source I_(C). The additionaltransistor Q_(C) provides a second dc mirror of transistor Q_(A) inwhich the Meyer correction is not applied, i.e. I_(C)=I_(A) andR_(C)=R_(A) and Q_(A) and Q_(C) are matched. Therefore the voltagebetween V_(A) and V_(C) will be equal to (V_(A)−V_(B))^(U). In this way,the difference in voltage between the emitters of transistors Q_(A) andQ_(C) can be used to obtain tanh((V_(A)−V_(B))^(U)/(2·V_(T))) forapplying the additional correction.

FIG. 4 is a schematic diagram of a circuit in which a tanh functionarises and from which a voltage correction ΔV ofk·I_(d)·tanh((V_(A)−V_(B))^(U)/(2V_(T))) can be produced. FIG. 4 showsan bipolar differential pair in which the emitters of two NPNtransistors Q_(D1) and Q_(D2) are coupled together and the emitters areconnected to ground via a current source I_(d), which is aproportional-to-absolute-temperature (PTAT) source. The collectors oftransistors Q_(D1) and Q_(D2) are coupled to a supply voltage Vcc viarespective resistors R_(D). The base voltage of Q_(D1) is V_(A),obtained from the emitter of transistor Q_(A) in the circuit of FIG. 3,and the base voltage of Q_(D2) is V_(C), obtained from the emitter oftransistor Q_(C) in the circuit of FIG. 3. The collector current ofQ_(D1) is I₁ and the collector current of Q_(D2) is I₂. It can be shownthat the difference in currents between the collectors of Q_(D2) andQ_(D1), I₂−I₁, is given by α_(F)·I_(d)·tanh((V_(A)−V_(C))/(2·V_(T))), inwhich α_(F) is the common-base current gain. Since α_(F) is close tounity, we can write that the difference in currents, I₂−I₁, isI_(d)·tanh((V_(A)−V_(C))/(2·V_(T))).

This difference in currents can be supplied to transistor Q_(B) toprovide current Icorr which, by which the additional voltage correctionΔV between V_(A) and V_(B) can be produced.

The circuits of FIGS. 2 and 3 provide the second voltage correction bydrawing a particular current at the base of the first referencetransistor Q_(B). Other circuits embodying aspects of the presentdisclosure may apply the correction via different means. Due to the holdcapacitor C_(A) of the detector, the detected voltage level and voltagecorrections are at a lower frequency than the RF signals. They representthe envelope or amplitude modulation of the RF signal. Therefore it maynot be necessary to consider RF operation of the means by which thecorrection is applied. As an example, voltage addition can be achievedusing a standard op amp voltage addition circuit, if the op amp canoperate at the modulation frequency of the envelope. This example is notexhaustive and other appropriate techniques for voltage addition will beapparent to the skilled reader.

FIG. 5 is a plot comparing the response at an operating temperature of313K (40° C.; approx. 104° F.) of an uncorrected detector, a detectorcorrected by Meyer's V_(T)·In(2) correction term, and a full correctionincluding Meyer's V_(T)·In(2) term and thek·I_(d)·tanh((V_(A)−V_(B))^(U)/(2·V_(T))) as provided in the circuits ofFIGS. 2, 3 and 4, to an ideal detector providing detected voltage levelVdet=Peak Vin over the range for RF input signals Vin having peakvoltages in the range 0V to 1.4V. The response voltage data of theuncorrected detector results from simulation data of a real diodedetector on a silicon-germanium process obtained using Cadence™electronic design software (Cadence Design Systems, Inc., CA, USA), thesimulated input RF signal having the form of a sine wave.

To simulate a detector incorporating Meyer's correction, V_(T)·In(2) wasevaluated at 313K and added to the Vdet values obtained for theuncorrected detector. To simulate the full correction, both Meyer'sV_(T)·In(2) term and k·I_(d)·tanh((Vdet/(2·V_(T))) were added to theVdet values obtained for the uncorrected detector. As k has dimensionsof resistance and is a somewhat empirical correction, this value wasadjusted to provide closest agreement with the ideal detector outputover the range. For high values of peak RF input signal Vin, thedetected voltages Vdet of the uncorrected detector, Meyer-correcteddetector and a detector incorporating the full correction, i.e. Meyerand the additional hyperbolic tangent correction, lie on or close to theline of an ideal detector, Vdet=Peak Vin. At lower levels of inputsignal, the uncorrected detector output falls significantly below theideal detector output. The Meyer-corrected detector and particularly thefully corrected detector appear to provide an output closer to the idealdetector at lower values of Vin.

FIG. 6 is a plot of the same data as FIG. 5 with the voltage level ofthe input signal limited to the range 0V to 0.5V to explore theperformance of the detectors at lower voltage levels. The simulationresults of the full correction lie on or close to the line of the idealdetector for almost the entire range input voltage range. The onlysignificant difference is at zero RF signal, when the Meyer correctionterm V_(T)·In(2) present in the full correction provides a non-zerooffset to Vdet. The Meyer detector also includes this correction termand so also has a non-zero offset to Vdet at zero RF input signal.However, the Meyer detector does not provide results as close to theideal detector as the fully corrected detector.

FIG. 7 is a plot of the magnitude of the error (“Error of uncorr.Det.”), i.e. difference in response, between the uncorrected detectoroperating at 313K and the ideal detector, as well as the differentcorrection terms used by the Meyer detector (“Meyer correction”) and afully corrected detector embodying an aspect of this disclosure (“Tanhcorrection” and “Meyer+Tanh correction”). The Meyer correction termV_(T)·In(2) is constant for all input voltage levels and appears as ahorizontal line at approximately 0.019V for the operating temperature of313K. While this correction reduces the error over the input signal peakvoltage range of 0V to 1.4V, FIG. 7 shows that there remains asignificant difference between the ideal detector output and theresponse of the Meyer-corrected detector.

The fully corrected detector includes an additional voltage correctionincluding a hyperbolic tangent term and FIG. 7 demonstrates that thisadditional voltage correction provides closer agreement with the errorbetween the uncorrected detector at 313K and the ideal detector in therange 0V to 0.5V, while falling off in absolute terms as Vin increases.However, the difference between the error term for the uncorrecteddetector and the combined voltage corrections of Meyer and theadditional hyperbolic tangent term remains smaller than the differencebetween the error term for the uncorrected detector and the Meyercorrection term alone over the whole voltage range 0V to 1.4V. FIG. 7therefore indicates that, at 313K at least, the additional voltagecorrection provides an improvement over the Meyer detector.

While the correction shown in FIG. 7 is includes a hyperbolic tangentterm, other corrections that are also based on the uncorrected detectoroutput, i.e. varying with input signal peak voltage level, may alsoprovide an improved detection relative to the Meyer correction. Forexample, in place of the hyperbolic tangent function, the a piecewisecorrection may be linearly increasing for input voltage levels from zeroincreasing up to a hard threshold, and then constant for input voltagelevels higher than the threshold. The hard threshold may be equivalentto an input signal peak voltage of about 0.1V, corresponding to around0.05 to 0.07V of the uncorrected detector output voltage, according tothe plot of FIG. 6. This correction may be implemented using anamplifier having a gain providing the initial slope for low values ofdetector output, the output of the being limited, for example bysaturation at the amplifier's supply voltages. As an alternative, anamplifier may use of gain compression to provide a higher gain for lowervalues of input voltage or soft limit, the gain reducing as the voltageincreases, either to zero or to a smaller gain than for the lower valuesof input voltage. Alternatively, another sigmoid curve may be appliedsuch as via an arctangent circuit although this might not necessarily beas conveniently realisable as the hyperbolic tangent function orpiecewise output-limited amplifier.

FIG. 7 shows that, in general, an additional correction beyond the Meyercorrection may provide an improved response for the simulated detector,the additional correction being based on the uncorrected detector outputand has a relatively high gain up to a threshold and a low or zero gainabove the threshold, the threshold being in the region of or varyinggradually over the range of about 0.1V to about 0.2V peak voltage ofinput signal, corresponding to about 0.05V to about 0.15V (orequivalently 50 to 150 mV) of uncorrected detector output voltageaccording to the graph uncorrected detector voltage against peak voltageof input signal in FIG. 6. Due to similar behaviour in other processesof bipolar transistors such as the simulated detector's NPN transistors,it is believed that an additional correction of this form may also beadvantageous to processes other than the silicon-germanium process inwhich the detector was simulated, although parameters such as themagnitude of the correction may need to vary to obtain the bestagreement with the ideal detector in processes other thansilicon-germanium. Nonetheless, a generalized correction of high gainfor uncorrected detector voltage below a threshold, low or zero gainabove the threshold, the threshold being in the region of or varyinggradually over the range of about 50 to about 150 mV, may feasibly stillprovide an improvement over the Meyer correction alone in processesother than silicon-germanium.

FIG. 8 is a plot showing the linearity of response of the uncorrecteddetector, Meyer detector and fully corrected detector at differentoperating temperatures. Vdet divided by Peak Vin is plotted against PeakVin for each of the uncorrected, Meyer and fully corrected detectors atsimulation temperatures of 253K, 313K and 373K (−20° C., 40° C. & 100°C.; approx. −4° F., 104° F. & 212° F.). Cadence™ simulation results wereobtained for a real diode detector at each of the simulationtemperatures, and thermal voltages for the correction voltages werecalculated according to the respective simulation temperature. For anideal detector having perfectly linear output, a plot of Vdet/Peak Vinagainst Peak Vin should provide a straight horizontal line at Vdet/PeakVin=1. The degree to which simulated results deviate from this linegives an indication of a detector's linearity of response or lackthereof. By including the results of different operating temperatures,the sensitivity of the linearity to temperature for each detector can beexplored. The plot of FIG. 8 is restricted to Peak Vin in the range 0Vto 0.5V because FIGS. 5 and 6 show that the lower end of the voltagerange is where the detectors tend to deviate most from linearity.

The results from the fully corrected detectors at all of the operatingtemperatures (solid lines) lie on or close to the horizontal lineVdet/Peak Vin=1 at all but the smallest Vin values, within the rangeVdet/Peak Vin=0.95 to 1.05 at all simulated temperatures down toVin=0.045V. By contrast, the Meyer detector remains within the rangeVdet/Peak Vin=0.95 to 1.05 only down to approximately Vin=1V (not shownin FIG. 8), within the broader range Vdet/Peak Vin=0.90 to 1.10 onlydown to Peak Vin=0.5V (not shown in FIG. 8), and within the broaderrange Vdet/Peak Vin=0.80 to 1.20 only down to Vin=0.16V. The uncorrecteddetector fairs worse in these simulations, being unable to remain withinthe Vdet/Peak Vin=0.95 to 1.05 range for all simulated temperatures atany of the simulated Vin values, within the broader range Vdet/PeakVin=0.90 to 1.10 only down to Vin=0.7V (not shown in FIG. 8), and withinthe broader range Vdet/Peak Vin=0.80 to 1.20 only down to Vin=0.3V. Fromthese simulation results, the fully corrected detector may offerimproved linearity over a broad range of operating temperatures comparedwith the Meyer detector and an uncorrected detector.

FIG. 9 is a flow diagram illustrating a technique embodying an aspect ofthe present disclosure. A method 100 of detecting a peak voltage of anRF input signal is illustrated, the method including a first step 110 ofrectifying an RF input signal with a detection transistor.

The second step 120 is to dc-offset the rectified RF signal using areference transistor. This may carried out by not supplying the inputsignal to the reference transistor that is otherwise set up and biasedin a similar to the detector transistor, at least for zero ac input.

The third step 130 is to generate a first correction voltage based onthe thermal voltage. The first voltage correction may be equal toV_(T)·In(2) and may be generated at a first reference transistor.Generating the first correction voltage may require that the firstreference transistor is not in fact biased identically to the detectortransistor for zero ac input as the correction will be provided even forzero ac input. Generating the first correction voltage may compriseoperating the first reference transistor at a higher current densitythan the average current density of the detection transistor.

The fourth step 140 is to generate a second correction voltage based onthe voltage difference between the detection transistor and a referencetransistor. This may be obtained without taking into account the firstvoltage correction. The second voltage correction may be based on asigmoid function of a voltage difference between the detectiontransistor and a second reference transistor that is not configured toreceive the RF input and may further be based on a hyperbolic tangent ofthe voltage difference between the detection transistor and the secondreference transistor divided by twice the thermal voltage. This may becarried out using a differential pair of transistors connected betweenthe detection transistor and the second reference transistor. The secondvoltage correction may also be generated at the first referencetransistor, which may involve the mirroring of a current of thecorrection to the first reference transistor.

The fifth step is to providing an output signal based on the voltagelevel of the RF input signal and the first and second correctionvoltages. This may be a differential output signal or a single-endedoutput signal relative to some datum such as a ground or supply voltage.

Steps of the method of FIG. 9 are not necessarily carried out insequence in the order of FIG. 9. The flow arrows of the flow diagram mayrepresent a conceptual flow of information helpful to the understandingof the method even through all steps take place simultaneously. Forexample, the dc-offsetting may take place in an electronic circuit atthe same time as the rectification of the RF signal, and the first andsecond correction voltages may also be generated simultaneously.

FIG. 10 is a schematic diagram of a circuit embodying an aspect of thepresent disclosure. Input nodes on the left-hand side are Vpos and Vneg,which are positive and negative supply inputs, VRF, which is the RFinput signal for which a peak voltage level is to be determined, andVbg, which is a band gap voltage reference. Output nodes on theright-hand side are Vref and Vposdet, between which the voltagedifference Vposdet-Vref is provided as the determined peak voltage levelof the RF input signal.

Vpos connects to the collectors of transistors Q1, Q25 and Q0, and toPFET mirror PM1 and PFET mirror PM2. Current source Icbias connectedbetween Vpos and a first internal node 210 provides a current from Vposto first internal node 210. VRF connects to the base of transistor Q0via capacitor C1. First internal node 210 is connected to the base oftransistor Q1 via resistor Rbias1, to the base of transistor Q1 viaresistor Rbias2 and to the base of transistor Q25 via resistor Rbias3.First internal node 210 is connected to Vneg via capacitor C2. Firstinternal node 210 is connected to second internal node 220 viatransistor Q26, by which the base and collector of transistor Q26 areconnected to first internal node 210 and the emitter of transistor Q26is connected to second internal node 220. The emitter of Q1 is connectedto output node Vref and to the collector of transistor Q2. The emitterof transistor Q0 is connected to output node Vposdet, to Vneg viacapacitor C3, and to the collector of transistor Q3.

The emitter of transistor Q0 is connected to the base of transistor Q23via resistor R22. The base of transistor Q23 is connected to Vneg viacapacitor C21. The emitter of transistor Q25 is connected to thecollector of transistor Q24. The emitter of transistor Q25 is connectedvia resistor R21 to the base of transistor Q22. The bases of transistorsQ2, Q3 and Q24 are connected to second internal node 220. SecondInternal node 220 is connected to the collector of transistor Q4 viaresistor R1. The collector of transistor Q4 is connected to its own basevia resistor R4. The emitter of transistor Q4 is connected to Vneg. Theemitter of transistor Q3 is connected to Vneg via resistors R3 a and R3b in series. The emitter of transistor Q2 is connected to Vneg viaresistors R2 a and R2 b in series. The emitter of transistor Q24 isconnected to Vneg via resistors R21 a and R21 b in series.

Input node Vbg is connected via resistor RPTAT2 to the collector oftransistor Q11. The bases of transistors Q11, Q12 and Q21 are alsoconnected to the collector of transistor Q11. The emitter of transistorQ11 is connected to Vneg via resistor RPTAT1. The emitter of transistorQ12 is connected to Vneg via resistor RPTAT3. The emitter of transistorQ21 is connected to Vneg via resistor RPTAT4. The collector oftransistor Q12 is connected to the base of transistor Q1.

The emitters of transistors Q22 and Q23 are connected together and tothe collector of transistor Q21. The emitter of transistor Q22 isconnected to a mirrored-current input node of PFET mirror PM1. Theemitter of transistor Q23 is connected to a mirrored-current input nodeof PFET mirror PM2. The mirrored-current input node of PFET mirror PM2is connected to a mirrored-current input node of NPN mirror NM1. Themirrored-current output node of PFET mirror PM1 is connected to amirrored-current output node of NPN mirror NM1 and to the base oftransistor Q1. NPN mirror NM1 is also separately connected to Vneg. Allof transistors Q0, Q1, Q2, Q3, Q4, Q11, Q12, Q21, Q22, Q23, Q24, Q25 andQ26 shown in FIG. 10 are NPN bipolar transistors.

FIG. 11 is a schematic diagram showing further circuit details of PFETmirrors PM1, PM2 and NPN mirror NM1 in the context of emitter-coupledtransistors Q22 and Q23. PFET mirror PM1 contains two PMOS transistorsQ32 and Q31 in a current-mirror configuration, with drains of each oftransistors Q32 and Q31 connected to Vpos. The gates of PMOS transistorsQ32 and Q31 are connected together and to the source of PMOS transistorQ31, which is connected to the emitter of NPN transistor Q22. In asimilar fashion, PFET mirror PM2 contains two PMOS transistors Q33 andQ34 in a current-mirror configuration, with drains of each oftransistors Q33 and Q34 connected to Vpos. The gates of PMOS transistorsQ33 and Q34 are connected together and to the source of PMOS transistorQ33, which is connected to the emitter of NPN transistor Q23.

NPN mirror NM1 contains two NPN transistors Q35 and Q36, the bases ofNPN transistors Q35 and Q36 being connected together and to the emitterof NPN transistor Q35. Emitter degeneration is present for each of NPNtransistors. The emitter of NPN transistor Q35 is connected to Vneg viaresistor RD2. The emitter of NPN transistor Q36 is connected to Vneg viaresistor RD1. The source of PMOS transistor Q34 in PMOS mirror PM2 isconnected to the emitter of NPN transistor Q35 in NPN mirror NM1. Thesource of PMOS transistor Q32 in PMOS mirror PM1 is connected to theemitter of NPN transistor Q36 in NPN mirror NM1, as well as to the baseof transistor Q1 (not shown).

In the circuit of FIG. 10, transistor Q0 is the detection transistorcorresponding to transistor Q_(A) in the circuit of FIG. 3. The emitterof Q0 provides the positive terminal Vposdet corresponding to terminalV_(A) in the circuit of FIG. 3, with capacitor C3 acting as the holdcapacitor to smooth the output between cycles of the RF input signal.The input RF signal enters the circuit at input node VRF, via decouplingcapacitor C1 and is supplied to the base of detection transistor Q0.

Transistor Q1 is a first reference transistor corresponding totransistor Q_(B) in the circuit of FIG. 3, used to dc provide theappropriate dc offset. As with the circuits of FIGS. 1 to 3, a voltagecorrection of V_(T)·In(2) is generated at the emitter of first referencetransistor Q1, but by a different method than proposed by Meyer andshown in FIGS. 1 to 3. Instead of being configured to have a currentdensity twice that of the detection transistor Q0 to generate thevoltage correction, the correction is provided by modifying the basecurrent to offset the voltage at the emitter. The offsetting current isprovided by PTAT current source of transistor Q12 to generate thevoltage offset of V_(T)·In(2).

Transistor Q25 is a second reference transistor corresponding totransistor Q_(C) in the circuit of FIG. 3. The Meyer voltage correctionof V_(T)·In(2) is not generated at the second reference transistor Q25and so the difference in emitter voltages between transistors Q0 and Q25is that which would have been obtained between transistors Q0 and Q1 ifthe V_(T)·In(2) voltage correction were not applied.

Capacitor C2 connecting between first internal node 210 and Vneg allowsthe high-frequency components of the measured RF input signal on VRF tobypass the rest of the circuit. This allows first and second referencetransistors Q1 and Q25 to act without the input of the RF signal.

Transistors Q22 and Q23 are in an emitter-coupled differential pairconfiguration, wherein the bases of Q22 and Q23 connect, via resistorsR21 and R22 respectively, to the emitters of second reference transistorQ25 and detection transistor Q0 respectively.

The purpose of resistor R22 between the emitter of detection transistorQ0 and the base of transistor Q23 of the differential pair is to actwith capacitor C21 between the base of Q23 and Vneg as a low-passfilter, to remove or reduce the effect of voltage ripple in the outputat the emitter of detection transistor Q0. Such ripple might arise dueto voltage drop from the charged capacitor when Q0 is not conducting. Tocompensate for the presence of resistor R22 between the base of thedifferential pair transistor Q23 and the emitter of detection transistorQ0, a corresponding resistor R21 is included between the emitter ofsecond reference transistor Q25 and the base of differential pairtransistor Q22.

As shown in FIG. 11, the difference in voltage between the bases of thedifferential pair transistors Q22 and Q23, arising from the differencein voltage between the emitters of detection transistor Q0 and secondreference transistor Q25, draws a current I₁ from PFET mirror PM1 and I₂from PFET mirror PM2. PFET mirror PM2 mirrors the current I₂ to a firstport of NPN mirror NM1 and PFET mirror PM1 mirrors the current I₁ to asecond port of the NPN mirror NM1. However, the NPN mirror NM1 is alsoconfigured to mirror the current I₂ from its first port to its secondport. Therefore at the junction between the PFET mirror PM1, the NPNmirror NM1 and a connection to the base of the first referencetransistor Q1 (not shown in FIG. 11), PFET mirror PM1 provides currentI1 to the junction mirrored from the collector of differential pairtransistor Q22, NPN mirror NM1 draws current I2 from the junctionmirrored via PFET mirror PM1 from the collector of differential pairtransistor Q23. As the currents to a junction are required to sum tozero, this causes a current to be drawn to the junction from the base ofthe first reference transistor Q1, the current drawn from the base of Q1by this connection being the differential current I₂−I₁.

The current drawn is proportional to the biasing current drawn from thecoupled emitters of differential pair transistors Q22 and Q23 and is thePTAT current multiplied by the hyperbolic tangent of the voltage ratioof the voltage difference between the emitters of detection transistorQO and second reference transistor Q25, which is not supplied by the RFsignal input and does not receive the V_(T) In(2) voltage offset,divided by twice the thermal voltage V_(T).

Transistors Q11, Q12 and Q21 provide proportional-to-absolute-temperature currents to bias the differential pair of transistors Q22and Q23 (via the collector of transistor Q21) and to cause the firstreference transistor Q1 to offset its emitter voltage by V_(T)·In(2).

Transistors Q2, Q3 and Q24 provide current sources for the detection andfirst and second reference transistors Q0, Q1 and Q25. Two seriesresistors R2 a/R2 b, R3 a/R3 b and R21 a/R21 b are provided between theemitters of Q2, Q3 and Q24 to allow tuning of the current source bycontrol of the resistors.

Transistor Q26 configured as a diode ensures a voltage drop betweenfirst internal node 210 and second internal node 220, thereby ensuring avoltage difference between the bases of e.g. the detection transistor Q0and its current source provided by Q3.

The detection transistor Q0 therefore operates according to the voltagelevel or peak voltage of the RF input signal at VRF. Capacitor C1ensures that no dc offset from the RF input arrives into the circuit.When the RF input signal is high, i.e. greater than zero, Q0 conducts,causing capacitor C3 to charge up. The capacitance of C3 is chosen togive appropriate degree of hold (i.e. time constant) over the RF inputsignal cycle between peaks, the particular value desired will depend onthe frequency or frequencies of operation. However, it may be assumedthat the stored energy of the capacitor ensures that the voltage remainsat the peak between cycles subject to any permitted voltage droop.

The detected signal level at Vposdet is measured relative to Vref,obtained from the emitter of first reference transistor Q1. Toincorporate the first and second voltage corrections into the detectedsignal level, two correction currents are supplied to the base of Q1.The first correction current is provided by theproportional-to-absolute-temperature current source from transistor Q12and generates a voltage correction of V_(T)·In(2). The second correctioncurrent is provided from the junction between first PFET mirror PM1 andthe NPN mirror NM1. The second correction current is proportional to thehyperbolic tangent function of the detected signal level relative toVref that would have been obtained in the absence of the first voltagecorrection, divided by twice the thermal voltage. By judicious choice ofcomponent values, the magnitude of the second voltage correction can bechosen to minimize the error between the detected peak voltage level andthe peak voltage of the input signal as would be detected by an idealdetector.

The circuit illustrated in FIG. 10 may be implemented in asilicon-germanium process. Other processes that may be suitable for theimplementation of detector circuits embodying an aspect of the presentdisclosure include silicon, germanium, gallium arsenide, indiumphosphide, indium gallium arsenide, gallium nitride and indium galliumnitride, although the circuit illustrated in FIG. 10 may require certainprocess-specific modifications that will be apparent to the skilledreader.

In some semiconductor processes, it may be relatively expensive toinclude PNP bipolar transistors and it is for this reason that the PFETcurrent mirrors are used in the circuits of FIGS. 10 and 11. Othercircuits embodying an aspect of the present disclosure implement somefeatures of the circuit of FIGS. 10 and 11 using PNP bipolartransistors.

While the differential pair of emitter-coupled bipolar transistorsprovides an efficient means to generate the desired hyperbolic tangentfunction, other functions may be appropriate if a sigmoid curve, i.e.S-shape, is obtained. Such functions include the logistic function andthe error function. An differential pair of FETs does not provide thesame hyperbolic tangent function as differential current output but bothFETs of the differential pair compete for a share of the biasing currentaccording to their gate voltages, the dc transfer function of thecurrent difference still having a sigmoid curve. Therefore, while thebipolar differential pair implementation may be a preferred feature of acircuit embodying an aspect of the present disclosure, circuits withoutthe bipolar differential pair implementation may nevertheless embodyaspects of the present disclosure.

While proportional-to-absolute-temperature current sources are includedin the circuit of FIGS. 10 and 11, and such current sources may beadvantageous in respect of the temperature variability of the detectorcircuit, such current sources are not a requirement of circuitsembodying aspects of the present disclosure. Other circuits embodyingaspects of the present disclosure do not include PTAT current sources orinclude some but not all of the PTAT current sources of FIGS. 10 and 11.

Certain other features of the circuit of FIGS. 10 and 11 will beapparent to the skilled reader as being non-essential to the detectionof a voltage level of an RF input signal according to aspects of thisdisclosure. Producing the first and second correction voltages betweenthe output nodes may be achieved in other ways that embody aspects ofthis disclosure. For example, the Meyer correction may be produced byproviding to transistor Q1 a current density that is greater than theaverage current density of the detection transistor Q0, as in thecircuits of FIGS. 1 to 3. This may be achieved by varying the sizes orscales of the first and second reference transistors Q1 and Q25 and thedetection transistor Q0 with respect to one another, or usingtransistors in parallel to produce a V_(T)·In(2) correction, or throughthe drawing of an increased current at the emitter as in the circuits ofFIGS. 1 to 3.

While the circuits of FIGS. 10 and 11 provide a differential output,other circuits embodying an aspect of the invention may provide asingle-ended output. For example, an additional differential pair may beconnected between the Vposdet and Vref output nodes of the circuit ofFIG. 10. In some embodiments according to an aspect of the presentdisclosure, the additional differential pair may be a differential pairwith active load. Other embodiments according to an aspect of thepresent disclosure include the use of an op amp to convert thedifferential output to a single-ended output.

In some embodiments, circuits of FIGS. 10 and 11, as well as FIGS. 2, 3and 4, are implemented as integrated circuits on a semiconductor die.This may provide advantages in regularity of device parameters acrossthe die as well as manufacturing advantages. Circuits embodying aspectsof the present disclosure may alternatively be implemented usingdiscrete components.

FIG. 12 schematically depicts an example RF system 300 according to anaspect of the present disclosure, the RF system 300 having a detector312 implemented to detect power at an output of a PA 304. The PA 304receives an RF signal to be transmitted from a transceiver 302. Theamplified RF signal from the 3A 104 is routed to an antenna 308 throughan antenna switching module (ASM) 306. In some embodiments of aspects ofthe present disclosure, such an amplification configuration isimplemented in a wireless local area network (WLAN) PA system.

FIG. 12 further shows that the detector 312 is coupled to thetransceiver 302. A control circuit in the transceiver 302 receives anoutput signal representative of the detected power from the detector314. Based on such an output signal, the RF signal generated by thetransceiver 302 is adjusted appropriately.

FIG. 13 shows an example of a packaged module 400 where a detector 112having one or more features as described herein is implemented on a die460 that is separate from a die 402 having a PA 304. In the example ofFIG. 6, both of the die 460, 402 are mounted on a packaging substrate450 that is configured to receive a plurality of components. Suchcomponents can include one or more die, such as the example die 460,402, as well as one or more surface mounted devices (SMDs) such aspassive components. In some embodiments, the packaging substrate 450 caninclude, for example, a laminate substrate.

In the example of FIG. 13, the die 460 includes a plurality ofelectrical contact pads 462 configured to allow formation of electricalconnections 464 such as wirebonds between the die 460 and contact pads466 formed on the packaging substrate 450. Similarly, the die 402 caninclude a plurality of electrical contact pads 452 configured to allowformation of electrical connections 454 such as wirebonds between thedie 402 and contact pads 456 formed on the packaging substrate 450.

FIG. 14 shows an example of a packaged module 400 where a detector 312having one or more features as described herein is implemented on a die470 that also includes a PA 304. In the example of FIG. 13, the die 470is mounted on a packaging substrate 450 that is configured to receive aplurality of components. Such components can include one or more die,such as the example die 470, as well as one or more surface mounteddevices (SMDs) such as passive components. In some embodiments, thepackaging substrate 450 can include a laminate substrate. In the exampleof FIG. 14, the die 470 includes a plurality of electrical contact pads452 configured to allow formation of electrical connections 454 such aswirebonds between the die 470 and contact pads 456 formed on thepackaging substrate 450.

In some embodiments, each of the modules 400 of FIGS. 13 and 14 alsoinclude one or more packaging structures to, for example, provideprotection and facilitate easier handling of the module 400. Such apackaging structure can include an overmold formed over the packagingsubstrate 450 and dimensioned to substantially encapsulate the variouscircuits and components implemented on the packaging substrate. It willbe understood that although the module 400 is described in the contextof wirebond-based electrical connections, one or more features of thepresent disclosure can also be implemented in other packagingconfigurations, including flip-chip configurations.

In some embodiments, a die having the PA 304 with its detector 312 isimplemented in a packaging configuration that does not necessarily relyon a laminate substrate. For example, such a die can be implementeddirectly in a QFN type package and not rely on a laminate.

It will also be understood that although the examples of FIGS. 13 and 14are described in the context of wirebond die, one or more features ofthe present disclosure can be implemented in other types of die. Forexample, a flip chip PA die can one or more detectors 314 as describedherein.

In some implementations, a device and/or a circuit having one or morefeatures described herein can be included in an RF device such as awireless device. Such a device and/or a circuit can be implementeddirectly in the wireless device, in a modular form as described herein,or in some combination thereof. In some embodiments, such a wirelessdevice can include, for example, a base station configured to providewireless services, a cellular phone, a smart-phone, a hand-held wirelessdevice with or without phone functionality, a wireless tablet, etc.

FIG. 15 schematically depicts an example wireless device 500 accordingto an aspect of the present disclosure. In the context of variousconfigurations described herein, one or more modules havingfunctionality depicted as 400 can be included in the wireless device500. As described herein, such a module can include functionalityassociated with a detector 312 having one or more features as describedherein, and functionality associated with a PA 104.

For example, a front-end module (FEM) 200 for WLAN/GPS operations caninclude a PA 304 and a detector 312 having one or more features asdescribed herein. Such a PA can be configured to amplify a WLAN signalfor transmission through an antenna 530. Such a WLAN signal can begenerated by a baseband sub-system 520 and routed to the FEM 400 througha WLAN/Bluetooth system-on-chip (SOC) 526.

In the example of FIG. 15, transmission and reception of

Bluetooth signals can be facilitated by an antenna 528. In the exampleshown, GPS functionality can be facilitated by the FEM 400 incommunication with a GPS antenna 532 and a GPS receiver 534.

In another example, an RF PA module depicted as 400 can include one ormore features as described herein. Such an RF PA module 400 can includeone or more bands, and each band can include one or more amplificationstages. One or more of such amplification stages can be in communicationwith one or more detectors (312) and benefit from the compensated powerdetection techniques as described herein.

In the example wireless device 500, the RF PA module 400 having aplurality of PAs 304 a-d can provide an amplified RF signal to a switch516 (via duplexer 514), and the switch 516 can route the amplified RFsignal to an antenna 508. The PA module 400 can receive an unamplifiedRF signal from a transceiver 502.

The transceiver 502 can also be configured to process received signals.Such received signals can be routed to an LNA (not shown) from theantenna 508, through the duplexer 514. As described herein, thetransceiver 502 can also include a controller configured to receive thedetected power signal and operate the transceiver 502 accordingly.

The transceiver 502 is shown to interact with a baseband sub-system 520that is configured to provide conversion between data and/or voicesignals suitable for a user and RF signals suitable for the transceiver502. The transceiver 502 is also shown to be connected to a powermanagement 318 that is configured to manage power for the operation ofthe wireless device 500. Such a power management component can alsocontrol operations of the baseband sub-system 520, as well as othercomponents.

The baseband sub-system 520 is shown to be connected to a user interface524 to facilitate various input and output of voice and/or data providedto and received from the user. The baseband sub-system 520 can also beconnected to a memory 522 that is configured to store data and/orinstructions to facilitate the operation of the wireless device, and/orto provide storage of information for the user.

A number of other wireless device configurations can utilize one or morefeatures described herein. For example, a wireless device does not needto be a multi-band device. In another example, a wireless device caninclude additional antennas such as diversity antenna, and additionalconnectivity features such as Wi-Fi, Bluetooth, and GPS. Circuits,semiconductor dies and RF modules according to aspects of thisdisclosure may be incorporated into devices having functionalityaccording to the following non-exhaustive list of standards: GlobalSystem for Mobile Communications (GSM), Second Generation (2G), GeneralPacket Radio Services (GPRS), Third Generation (3G), Third GenerationPartnership Project (3GPP), Enhanced Data Rates for GSM Evolution(EDGE), Fourth Generation (4G) (Mobile WiMax and LTE) and Wideband CodeDivision Multiple Access (W-CDMA), among other high band and low bandstandards. Circuits, semiconductor dies and RF modules according toaspects of this disclosure may also be incorporated into devices havingfunctionality according to IEEE 802.11 specifications for wireless localarea network (WLAN) communication.

In interpreting the disclosure, all terms should be interpreted in thebroadest possible manner consistent with the context. In particular, theterms “comprises” and “comprising” should be interpreted as referring toelements, components, or steps in a non-exclusive manner, indicatingthat the referenced elements, components, or steps may be present, orutilized, or combined with other elements, components, or steps that arenot expressly referenced. In the context of this disclosure, the term“based on” does not mean “based only on,” unless expressly specifiedotherwise. In other words, the term “based on” describes both “basedonly on” and “based at least on.” The term “determining” encompasses awide variety of actions and, therefore, “determining” can includecalculating, computing, processing, deriving, investigating, looking up(e.g., looking up in a table, a database or another data structure),ascertaining and the like. Also, “determining” can include receiving(e.g., receiving information), accessing (e.g., accessing data in amemory) and the like. Also, “determining” can include resolving,selecting, choosing, establishing and the like.

The methods, process and algorithms that have been described may bestored as one or more instructions on a processor-readable orcomputer-readable medium. The term “computer-readable medium” refers toany available medium that can be accessed by a computer or processor. Byway of example, and not limitation, such a medium may comprise RAM, ROM,EEPROM, flash memory, CD-ROM or other optical disk storage, magneticdisk storage or other magnetic storage devices, or any other medium thatcan be used to store desired program code in the form of instructions ordata structures and that can be accessed by a computer. Disk and disc,as used herein, includes compact disc (CD), laser disc, optical disc,digital versatile disc (DVD), floppy disk and Blu-ray® disc where disksusually reproduce data magnetically, while discs reproduce dataoptically with lasers. It should be noted that a computer-readablemedium may be tangible and non-transitory. In the context of thisdisclosure, the term “code” may refer to software, instructions, code ordata that is/are executable by a computing device or processor.

Software or instructions or data may also be transmitted over atransmission medium. For example, if the software is transmitted from awebsite, server, or other remote source using a coaxial cable, fibreoptic cable, twisted pair, digital subscriber line (DSL), or wirelesstechnologies such as infrared, radio, and microwave, then the coaxialcable, fibre optic cable, twisted pair, DSL, or wireless technologiessuch as infrared, radio, and microwave are included in the definition oftransmission medium.

The above detailed description of embodiments of the invention is notintended to be exhaustive or to limit the invention to the precise formdisclosed above. While specific embodiments of, and examples for, theinvention are described above for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example, whileprocesses or blocks are presented in a given order, alternativeembodiments may perform routines having steps, or employ systems havingblocks, in a different order, and some processes or blocks may bedeleted, moved, added, subdivided, combined, and/or modified. Each ofthese processes or blocks may be implemented in a variety of differentways. Also, while processes or blocks are at times shown as beingperformed in series, these processes or blocks may instead be performedin parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

The headings provided herein are for convenience only and do notnecessarily affect the scope or meaning of the aspects of this thedisclosure defined by the claims.

Some embodiments have been described. These embodiments are presented byway of example only and are not intended to limit the scope of thedisclosure. Indeed, the novel methods, apparatus and systems describedherein may be embodied in a variety of other forms. It should beapparent to those skilled in the art that many more modificationsbesides those already described are possible without departing from theinventive concepts herein. Furthermore, various omissions, substitutionsand changes in the form of the methods and systems described herein maybe made without departing from the spirit of the disclosure. Theaccompanying claims and their equivalents are intended to cover suchforms or modifications as would fall within the scope and spirit of thedisclosure.

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The word “coupled”, as generally usedherein, refers to two or more elements that may be either directlyconnected, or connected by way of one or more intermediate elements.Additionally, the words “herein,” “above,” “below,” and words of similarimport, when used in this application, shall refer to this applicationas a whole and not to any particular portions of this application. Wherethe context permits, words in the above Description using the singularor plural number may also include the plural or singular numberrespectively. The word “or” in reference to a list of two or more items,that word covers all of the following interpretations of the word: anyof the items in the list, all of the items in the list, and anycombination of the items in the list.

The above detailed description of embodiments of the invention is notintended to be exhaustive or to limit the invention to the precise formdisclosed above. While specific embodiments of, and examples for, theinvention are described above for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example, whileprocesses or blocks are presented in a given order, alternativeembodiments may perform routines having steps, or employ systems havingblocks, in a different order, and some processes or blocks may bedeleted, moved, added, subdivided, combined, and/or modified. Each ofthese processes or blocks may be implemented in a variety of differentways. Also, while processes or blocks are at times shown as beingperformed in series, these processes or blocks may instead be performedin parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

While some embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the disclosure. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the disclosure.

What is claimed is:
 1. A method of detecting a voltage level of aradio-frequency input signal, the method comprising: rectifying theradio-frequency input signal with a detection transistor; dc-offsettingthe rectified radio-frequency input signal using a reference transistorthat is not configured to receive the radio-frequency input signal;generating a first correction voltage based on the thermal voltage;generating a second correction voltage that is based on a voltagedifference between the detection transistor and the referencetransistor; and providing an output signal based on the voltage level ofthe radio-frequency input signal and the first and second correctionvoltages.